In the fields of electronics and electrical devices, most manufactured products comprise a variety of sub-components that require interconnection. For many products the number of these sub-components can be very large while the overall size of the manufactured product is relatively small. This is particularly true for electronic goods, which typically comprise mounting boards (e.g. printed circuit boards) that facilitate the interconnection of many semiconductor chips and other electrical components. Each component on such a mounting board may have numerous connectors (from just a few to several hundred), making the task of interconnections a challenge, even in the absence of constraints such as size and electrical characteristics.
Due to the nature of electronics design, mounting boards (such as printed circuit boards) often carry several functionally identical components. For example a contemporary memory DIMM board may carry several identical DRAM chips. Many of the connectors on these chips are common to all identical chips on the board (e.g. data, address, clock, reset, power and ground connectors). Referring to FIG. 17, there are shown two normal 16-lead quad packages for which anyone might imagine the difficulty of interconnecting identically-numbered leads (i.e. pin 1 chip A to pin1 chip B, pin 2 chip A to pin 2 chip B, pin 3 chip A to pin 3 chip B, and so on). In whatever interconnection scheme one might imagine, there will be crossed lines (connections) and/or lines running under the chips (between leads). For each place that lines cross, there is possible need of a via (connection through lower layers of the board) to make the interconnect in practice. As is evident in FIG. 17, substantial under-chip connections or via connectors will be necessary to connect common leads on two simple 16-lead devices. The problem exists to a lesser extent in smaller chips (such as an 8 pin dip) and compounds dramatically as the lead count and complexity of the chips increases (e.g. larger quad packs and BGAs). The problem is yet further exacerbated by two-sided configurations as shown in FIG. 5. Referring to FIG. 5, there is shown a mounting board 503. The mounting board 503 has three identical chips for mounting, two on top of the mounting board (chips 501 and 502); and one on the bottom of the mounting board (chip 504). It is evident that there is tremendous complexity in connecting the common numbered leads of the three chips pictured in FIG. 5 (chips 501 and 504 are shown tilted to indicate their relationship of top over bottom).
Without digressing into great detail that is well know in the art, the cost of mounting board design and manufacture rises with the complexity of the interconnections discussed. This is generally because of the number of layers and vias required to make interconnections without violating electrical specifications for such issues as cross-talk, impedance, inductance or capacitance.
In summary, the current state of the art is that surface mount and double-sided surface mount configurations are being used as an alternative to old through-hole PC boards. For a single type of chip. the chip suppliers generally only offer packages with the one pin-out (the configuration of leads around the chip and the correspondence of those leads to the functional elements of the chip). Therefore, board designers are faced with the problem illustrated in FIGS. 5 and 17, with the exception that the chips more typically have dozens or hundreds of leads that are packaged extremely densely. The results are (i) board designs that are monumental three dimensional problems; (ii) high costs to boards due to multiple layers, complex interconnects and design effort; and (iii) the failure of many products to come to market because layout complexities violate specifications, standards or cost constraints (e.g. testing failures).
There have been efforts to mitigate these problems, however, none have been terribly useful and widely commercialized. A prominent example of a common mitigation technique is to re-orient one or more chips on board so that common connections may be made more easily. This technique has limited efficacy (especially on high-lead-count designs) and generally increases the required board space. Another example is discussed in U.S. Pat. No. 5,502,621, which proposes a chip packaging design to aggregate functions in “mirror image” lead assignments. In particular, the '621 Patent proposes that two identical “mirror image” chips may be used to make board routing easier. This is simply a variation of the re-orientation technique. However, in addition to re-orienting the positioning of a chips on a board, the '621 Patent proposes re-orienting the position of leads on a chip, so that multiples of such chip may be more easily interconnected. Similarly, in the process of disclosing a test-related invention, U.S. Pat. No. 6,442,056 proposes classification of leads on a chip by their functional grouping (e.g. power, input output, input only etc.). In so proposing, the '056 Patent states that the “function assignment arrangement of a packaged semiconductor device according to the present invention is identical to the function assignment arrangement of a mirror image of that packaged semiconductor device” (Column 5, lines 4-8). The '056 Patent goes on to suggest that, if a test device shares the functional regions of the suggested semiconductor chips, the same test device may be used to test both members of a mirrored pair (Column 5, lines 26-28). Therefore, no damage would be caused if the wrong part of a mirrored pair was put in a tester because all the same functional sections would exist on the test head (Column 5, lines 56-64).
While these three alternative techniques may provide some mitigation to the layout and mounting problems discussed, there remains a need for further simplification. For example, there remains a need for parts with three or more common connections to be manufactured such that board layout and design are greatly simplified.